SystemVerilog Assertions (SVA) can be used to implement relatively complex functional coverage models under appropriate circumstances. This paper explores the issues and implementation of such a functional coverage model to demonstrate both the capabilities of SVA coverage and illustrate coding techniques which can also be applied to the more typical use of SVA coverage, which is to specify key corner cases for the RTL from the designer’s detailed knowledge of the structural implementation. This paper is related to previous work published at SNUG Europe 2005 called Utilizing Vera Functional Coverage in the Verification of a Protocol Engine for the FlexRayTM Automotive Communication System; readers are encouraged to read both papers. DAC 2005 (white paper presented on Accellera booth).

( Mark Litterick )