At Verilab we help our clients find and fix design and specification bugs, before going into production. We develop reusable verification environments, rescue projects struggling with verification, develop sophisticated verification IP, re-engineer methodologies, manage projects, review, audit, coach and train. Our expertise spans multiple verification specific languages and methodologies for digital and mixed-signal, including SystemVerilog, UVM, Specman/e, VHDL and Verilog-AMS. We have flexible engagement models for staff augmentation and turnkey development.
Verilab has developed a combination of hardware and software skills and brought these to bear on the increasingly complex problem of functional verification in ASIC and FPGA systems. Examples of our team’s skills include:
► RTL design and verification
► Constrained-random, coverage-driven verification
► Reusable object-oriented verification solutions
► SystemVerilog, Verilog-AMS, e/Specman, VHDL, C/C++, Python, UVM, eRM
► Assertion-Based Verification
► Formal Verification CDC/RDC design and verification
► Mixed-signal verification
► Requirements-based verification
► Planning and management (Agile/SCRUM and traditional)
► Continuous Integration (e.g. Jenkins) and regression environments
► Numerous CPU and DSPs including ARM
► Audit and forensic reviews
► Workshops and training
We have condensed various key aspects of our expertise into intensive workshops aiming to rapidly increase the capability of our clients’ engineering teams. Examples include:
► Advanced UVM
► Verification planning and management
► Requirements-based verification process
► Clock Domain Crossing design and verification
Using the experience gained over this wide range of application areas, we are able to face verification challenges with confidence and consistency. Some of these experiences have been captured in papers and presentations available from our website.
