Best Paper Award

Recent advances in automated formal solutions for verification of clock domain crossing signals go far towards reducing the risk of clock related defects in multi-clock system-on-chip devices. However the vast majority of multiple clock-domain devices still utilize a flow which does not involve these specialized tools or formal verification techniques. This paper presents a pragmatic alternative methodology, using SystemVerilog Assertions in a simulation-based verification flow, to validate the correct operation and use of synchronizers while emulating the effects of CDC jitter in order to stress the functional operation of the rest of the device.

( Mark Litterick )