DVCon 2013: Run-time Configuration of a Verification Environment - A Novel Use of the OVM/UVM Analysis Pattern

Paper

Poster

This paper describes a novel approach to modeling the real-time variation of delays required for the functional verification of a DIMM (Dual In-Line Memory Module) system consisting of DDR3 memory and other interface devices using an OVM environments analysis pattern to provide run-time delay control. The system requirements could not be verified without the ability to provide temporal control of the delay elements in the environment. Different approaches to solving this problem were examined before determining the solution adopted was the best fit for the task at hand.  

( Paul Marriott , Mark Ronan )

Created  
February 26, 2013
#OVM #DVCON_US