Best Paper Award

Complex protocol checks in Universal Verification Methodology Verification Components are often implemented using SystemVerilog Assertions; however, concurrent assertions are not allowed in SystemVerilog classes, so these assertions must be implemented in the only non-class based "object" available, the interface construct. This creates problems of encapsulation (since the verbose assertion code clutters the interface definition) and isolation (since the assertions depend on aspects of class configuration and operation). This paper demonstrates several pragmatic solutions for encapsulation and operation of assertions including mechanisms to make the assertions aware of the configuration and phases of the class-based verification environment.

( Mark Litterick )