As the language of choice for many verification engineers, SystemVerilog is expected to act not only as a specialist verification language, but also as a hardware description language and a general purpose programming language. Although SystemVerilog's object oriented programming features and rich set of native data types provide excellent support for general purpose programming, many users including the authors have been frustrated by its lack of utility features that would be taken for granted in other languages. In this paper we present the results of our efforts to develop a comprehensive, consistent, easy-to-use utility library for SystemVerilog. We believe this to be the first announcement of such a library that is vendor-independent and carefully tailored to the needs of SystemVerilog users.

Code download and more information at svlib

( Jonathan Bromley , André Winkelmann )