This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner. Maximizing leverage of a known-answer-test strategy, based on predefined data scenarios combined with design-for-verification modes, we demonstrate how to find and isolate concept and design bugs early in the flow. This approach allows us to postpone detailed integration of complex mathematical models until much later in the RTL development. The solutions presented are based on real project experience with single chip radar sensors for a variety of applications. The verification environments supporting the presented strategies are based on SystemVerilog and the Universal Verification Methodology.

Mark Litterick, Verilab, Munich, Germany

Aleksandar Ivankovic, Verilab, Belgrade, Serbia

Bojan Arsov, Verilab, Belgrade, Serbia

Aman Kumar, Infineon Technologies, Dresden, Germany

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