This tutorial provides intermediate and advanced users of the Universal Verification Methodology (UVM) with comprehensive in-depth material on all aspects of achieving vertical and horizontal verification reuse using UVM. The content is derived from Verilab’s extensive experience in solving reuse issues for many different clients, projects and applications using a variety of verification languages and includes pragmatic guidelines as well as real-world examples. It is aimed at engineers with a good understanding of SystemVerilog and practical experience in either OVM or UVM. UVM beginners may also find the content interesting although the details could be somewhat overwhelming, at any rate it should raise awareness and provide some good reference material for the future. The material is grouped into the following topics:

• Part 1: Vertical & Horizontal Reuse of UVM Environments
• Part 2: Self-Tuning Functional Coverage - Strategy & Implementation
• Part 3: Adaptive Protocol Checks - Configuration Aware Assertions
• Part 4: Configuration Object Encapsulation & Appropriate config_db Usage
• Part 5: Parameterized Classes, Interfaces & Registers

( Jason Sprott , Mark Litterick , Jonathan Bromley )