DVCon Europe 2015 - Best Paper Award

Also presented at SNUG Austin 2015 and MTV Austin 2015.

Pairwise, and more generally N-wise, pattern generation has long been known as an efficient and effective way to construct test stimulus and configurations for software testing. It is also highly applicable to digital design verification, where it can dramatically reduce the number and length of tests that need to be run in order to exercise a design under test adequately. Unfortunately, readily available tools for N-wise pattern generation do not fit conveniently into a standard hardware verification flow. This paper reviews the background to N-wise testing, and presents a new open-source SystemVerilog package that leverages the language's constrained randomization features to offer flexible and convenient N-wise generation in a pure SystemVerilog environment.

The paper and presentation here are the versions that appeared at DVCon-Europe in November 2015. A freely downloadable SystemVerilog code package is included.

( Kevin Johnston , Jonathan Bromley )