The Universal Verification Methodology (UVM) has brought extensive benefits to the field of functional verification using SystemVerilog. However, applying it to real projects can bring challenges and frustrations for novice and intermediate-level users. This paper examines typical examples of such challenges, and offers solutions that respect fundamental aims of the UVM: consistency, reusability, and expressive power. Examples include integration of directed tests or external models into the sequences mechanism, reconciling the abstract and untimed nature of sequences with the need for precise control over stimulus timing, proper use of the configuration or resource databases and when it is better not to use them, and working with a parameterized device under test.

( Jonathan Bromley )