The Universal-Verification-Methodology Multi-language (UVM-ML) library is a simulator independent extension of the UVM and promises easy integration of different high-level verification languages. We applied it together with previously existing techniques to attach a SystemC model to different UVM SystemVerilog testbenches. The interface between the two worlds has been implemented using TLM2, DPI-C, and FMI. Over the course of this project we faced some obstacles and stumbling blocks concerning different aspects. By sharing our experience and some tips and hints, we hope to provide others with a smoother experience.

( Thorsten Dworzak , Angel Hidalga )