This paper demonstrates a technique that allows a single UVM testbench to adapt to design configuration changes that would otherwise require significant manual effort. The solution accommodates multiple design versions, changes in design hierarchy, and testbench migrations to future project iterations. It also allows us to simulate any subsystem in isolation without maintaining a separate testbench. To achieve this, we show several enhancements to the UVM harness technique along with a run-time generated environment topology that mirrors the design hierarchy. Examples show how this results in a testbench that automatically adapts and works with any design configuration.

( Jeff Vance , Jeff Montesano , Kevin Johnston , Kevin Vasconsellos )