Technical Committee Best Paper award at SNUG Silicon Valley 2014
Creative use of the constraint solver built in to your SystemVerilog simulator can not only provide valuable random stimulus, but also can offer a highly productive way to solve certain programming problems. This paper looks at SystemVerilog randomization from a novel perspective, considering it not so much as a way to generate random numbers, but as a flexible and intuitive way to find a set of values that satisfy user-specified rules (constraints).

( Paul Marriott , Jonathan Bromley )