The clocking block feature was designed to provide SystemVerilog verification environments with a versatile and well-structured way to access synchronous signals in a DUT or test harness. In practice, though, the use of clocking blocks has proved to be surprisingly error-prone, despite nearly a decade of application experience since they were first standardized.

This paper reviews the key features and purpose of clocking blocks and then examines why they continue to be a source of confusion and unexpected behavior for many verification engineers. Drawing from the authors’ project and mentoring experience, it highlights typical usage errors and how to avoid them. We clarify the internal behavior of clocking blocks to help engineers understand the reasons behind common problems, and show best-practice techniques that allow clocking blocks to be used productively and with confidence. Finally, we consider some areas that may cause portability problems and indicate how to avoid them.

( Kevin Johnston , Jonathan Bromley )