The topic of register models, configuration objects, and their interaction can be an area of great complexity and sometimes confusion for many verification engineers. Fundamentally, a register model holds the contents of each register in the design for use by the verification environment, while a configuration object holds the configuration for the interface protocol agents, verification components and verification environment.  So while one is implementation specific (register model) and one is generic (configuration object), they both hold configuration information and are both required in a given testbench.  In this paper we will describe the unique roles of register models and configuration objects, explain why they should both be used in a verification environment, and present a framework in SystemVerilog/UVM for making the testbench and design configurations remain in sync for different types of designs.

( Jeff Vance , Jeff Montesano )