Technical Committee Award for Best Paper

Universal Verification Methodology (UVM) sequences are the standard way of controlling scenarios for design verification. Presently, no methodology exists to define an optimal collection of sequences for a UVC (UVM verification component) and/or a UVM testbench. A sub-optimal sequence library typically leads to overly complex testbenches that are hard to control, debug, and maintain. These problems pose risks to both project schedule and tapeout quality. This paper presents guidelines that solve these problems. We show how to isolate constraint solver steps through sequence application programming interface (API) layers that lead to rapid debug, improved sequence reuse, and easier control for test writers. Encapsulation guidelines demonstrate how to enhance sequences using configuration objects and package utility methods. Many of these guidelines come from extensive project experience dealing with complicated problems that occur on a large scale.

(Jeff Vance , Jeff Montesano , Mark Litterick)