RTL parameters are used frequently in designs, especially IPs, in order to increase flexibility for reuse or different target applications and products. As demand for feature density or power efficiency increases, the number of permutations of valid RTL parameters becomes increasingly difficult to manage. A well structured and flexible verification testbench is therefore required to handle the multiplicity of combinations of these parameters. Failure to account for this could result in a testbench that would become difficult to maintain, or, worse, no longer adequate to find potential bugs in all possible permutations of the parameters. This paper proposes solutions for structuring various segments of a UVM test bench to handle designs with large amounts of DUT parameter combinations, minimizing maintenance effort and risk of bug escapes.  

( Alex Melikian , Paul Marriott )