UVM's register package has an "active monitoring" feature that allows you to predict the value of read-only status registers by probing the HDL signal that carries that status.  Until now, detecting value-changes on those status signals has been tricky, requiring hard-coded cross-module references that don't sit nicely with the configurability that we expect from a UVM test environment. This paper presents a novel SystemVerilog VPI/DPI package that cuts through this problem, allowing the signal's name to be specified as a string and removing all need for hard-coded references.  It's also great for monitoring other miscellaneous status signals in your UVM, OVM or VMM testbench, even if you're not using a register package.  We're already using this new package in our own projects.  Code, paper and presentation are all available for download here.

( Jonathan Bromley )