The proper testing of most digital designs requires that error conditions be stimulated to verify that the design either handles them in the expected fashion, or ignores them, but in all cases recovers gracefully.  A self-checking constrained-random environment can be put to the test when injecting errors, because unlike the device-under-test (DUT) which can potentially ignore an error, the testbench is required to recognize it, potentially classify it, and determine an appropriate response from the design.  In this paper we will present an error injection strategy using UVM that meets all of these requirements.  The strategy encompasses both active and reactive components, with code examples provided to illustrate the implementation details.

( Jeff Montesano , Mark Litterick )