This paper describes a novel, more complete approach to functional verification of sub-cycle timing using SystemVerilog assertions in an OVM verification environment. This approach found many bugs otherwise missed in OVM-only simulations. This functional sub-cycle timing behaviour includes maintaining fixed delays and phase relation- ships between inputs and outputs and ensuring there are no glitches on clocks or delayed signals. SystemVerilog assertions are evaluated on successive occurrences of an event or timing expres- sion. This presents a challenge for sub-cycle timing verification, where there is no obvious ref- erence clock suitable for triggering the assertions. Assertions sample their expressions in the preponed region of the simulation time slot, but the requirements called for sampling both before and after each triggering point. Examples of assertions showing how to overcome this and many other issues will be shown along with recommendations on how to write assertions for functional timing verification.

( Anders Nordstrom )