Technical Committee Honourable Mention Award

The design and coding of SystemVerilog covergroups can be laborious and error-prone, partly because of the inherent difficulty of the task, but also because the language's features have traditionally provided limited support for configurable and reusable coverage. Fortunately, support is now available in VCS and other simulators for many of the interesting coverage features introduced in the 2012 revision of SystemVerilog. We give examples, guidelines and recommendations showing how these features can make your code more concise, expressive and versatile. The Universal Verification Methodology brings its own special considerations, so the paper also offers specific coding patterns for configurable and reusable coverage within UVM testbench classes.

(Also included in SNUG Austin 2016 proceedings.)

( Jonathan Bromley , Mark Litterick, Vanessa Cooper )