Have you ever thought "why do I have to use all these uvm_field_* macros when I’ve already declared my transaction variables ?”. Or "what on earth is trans::type_id::create” ? Or "why are there so many types of uvm_do macros ?”. This white paper makes a number of related suggestions to improve SystemVerilog and bring it up to date with recent developments in languages such python and C++.

( Adam Rose )