SNUG Austin 2018: Use the Sequence, Luke - Guidelines to Reach the Full Potential of UVM Sequences
Presentations
Universal Verification Methodology (UVM) sequences are the standard way of controlling scenarios for design verification. Presently, no methodology exists to define an optimal collection of sequences for a UVC (UVM verification component) and/or a UVM testbench. A sub-optimal sequence library typically leads to overly complex testbenches that are hard to control, debug, and maintain. These problems pose risks to both project schedule and tapeout quality. This paper presents guidelines that solve these problems. (Jeff Vance , Jeff Montesano , Mark Litterick)
October 23, 2018
Presentations
#UVM #AWARD
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